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mosel vitelic 1 V53C806H high performance 1m x 8 bit fast page mode cmos dynamic ram preliminary V53C806H rev. 1.6 february 1999 high performance 40 45 50 60 max. ras access time, (t rac ) 40 ns 45 ns 50 ns 60 ns max. column address access time, (t caa ) 20 ns 22 ns 24 ns 30 ns min. fast page mode cycle time, (t pc ) 23 ns 25 ns 28 ns 40 ns min. read/write cycle time, (t rc ) 75 ns 80 ns 90 ns 120 ns features n 1m x 8-bit organization n fast page mode for a sustained data rate of 43 mhz n ras access time: 40, 45, 50, 60 ns n read-modify-write, ras -only refresh, cas -before-ras refresh capability n refresh interval: 1024 cycle/16 ms n available in 28-pin 400 mil soj package n single +5v 10% power supply n ttl interface description the V53C806H is a ultra high speed 1,048,576 x 8 bit cmos dynamic random access memory. the V53C806H offers a combination of features: fast page mode for high data bandwidth, and low cmos standby current. all inputs and outputs are ttl compatible. input and output capacitances are significantly lowered to allow increased system performance. fast page mode operation allows random access of up to 1024 x 8 bits within a row with cycle times as fast as 23 ns. because of static circuitry, the cas clock is not in the critical timing path. the flow-through col- umn address latches allow address pipelining while relaxing many critical system timing requirements. the V53C806H is ideally suited for graphics, dig- ital signal processing and high-performance com- puting systems. device usage chart operating temperature range package outline access time (ns) power temperature mark k 40 45 50 60 std. 0 c to 70 c blank
2 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H family device pkg ( t rac ) speed pwr. v 5 3 c 40 (40 ns) 45 (45 ns) 50 (50 ns) 60 (60 ns) temp. blank (0 c to 70 c) blank (normal) k (soj) 8 0 6 h 808h-01 description pkg. pin count soj k 28 28-pin soj pin configuration top view pin names v cc io1 io2 io3 io4 we nc nc a0 a1 a2 a3 1 2 3 4 5 6 8 9 10 11 12 13 28 27 806h-02 26 25 24 23 21 20 19 18 17 v ss io8 io7 io6 io5 cas a9 a8 a7 a6 a5 a4 16 ras v cc 7 14 22 oe v ss 15 a 0 ? 9 address inputs ras row address strobe cas column address strobe we write enable oe output enable i/o 1 ?/o 8 data input, output v cc +5v supply v ss 0v supply nc no connect absolute maximum ratings* ambient temperature under bias .................................. ?0 c to +80 c storage temperature (plastic) ...... ?5 c to +125 c voltage relative to v ss ................. ?.0 v to +7.0 v data output current ..................................... 50 ma power dissipation .......................................... 1.4 w *note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v cc = 5 v 10%, f = 1 mhz * note: capacitance is sampled and not 100% tested symbol parameter typ. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 4 5 pf c out data input/output 5 7 pf
3 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H block diagram a 0 a 1 a 8 a 9 sense amplifiers refresh counter v cc v ss 10 i/o 1 address buffers and predecoders x 0 -x row decoders 1024 memory array 1024 x 1024 x 8 column decoders data i/o bus y 0 -y 9 1024 x 8 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock 1m x 8 generator ras clock generator oe 806h-03 we cas ras 9 i/o 5 i/o 6 i/o 7 i/o 8
4 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H dc and operating characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time V53C806H unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m a v ss v in v cc i lo output leakage current (for high-z state) ?0 10 m a v ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 40 220 ma t rc = t rc (min.) 1, 2 45 210 50 200 60 190 i cc2 v cc supply current, ttl standby 4 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 40 220 ma t rc = t rc (min.) 2 45 210 50 200 60 190 i cc4 v cc supply current, fast page mode operation 40 110 ma minimum cycle 1, 2 45 100 50 90 60 80 i cc5 v cc supply current, standby, output enabled 2.0 ma ras = v ih , cas = v il other inputs 3 v ss 1 i cc6 v cc supply current, cmos standby 2.0 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss v cc supply voltage 4.5 5.0 5.5 v v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 v i oh = ? ma
5 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter 40 45 50 60 unit notes min. max. min. max. min. max. min. max. 1 t ras ras pulse width 40 75k 45 75k 50 75k 60 75k ns 2 t rc read or write cycle time 75 80 90 110 ns 3 t rp ras precharge time 25 25 30 40 ns 4 t csh cas hold time 40 45 50 60 ns 5 t cas cas pulse width 12 13 14 15 ns 6 t rcd ras to cas delay 17 28 18 32 19 36 20 43 ns 7 t rcs read command setup time 0 0 0 0 ns 4 8 t asr row address setup time 0 0 0 0 ns 9 t rah row address hold time 7 8 9 10 ns 10 t asc column address setup time 0 0 0 0 ns 11 t cah column address hold time 5 6 7 10 ns 12 t rsh (r) ras hold time (read cycle) 12 13 14 15 ns 13 t crp cas to ras precharge time 5 5 5 5 ns 14 t rch read command hold time referenced to cas 0 0 0 0 ns 5 15 t rrh read command hold time referenced to ras 0 0 0 0 ns 5 16 t roh ras hold time referenced to oe 8 9 10 10 ns 17 t oac access time from oe 12 13 14 17 ns 18 t cac access time from cas 12 13 14 17 ns 6, 7 19 t rac access time from ras 40 45 50 60 ns 6, 8, 9 20 t caa access time from column address 20 22 24 30 ns 6, 7, 10 21 t lz cas to low-z output 0 0 0 0 ns 16 22 t hz output buffer turn-off delay time 0 6 0 7 0 8 0 10 ns 16 23 t ar column address hold time from ras 30 35 40 45 ns 24 t rad ras to column address 12 20 13 23 14 26 15 30 ns 11 delay time 25 t rsh (w) ras or cas hold time in write cycle 12 13 14 15 ns 26 t cwl write command to cas lead time 12 13 14 15 ns 27 t wcs write command setup time 0 0 0 0 ns 12, 13 28 t wch write command hold time 5 6 7 10 ns 29 t wp write pulse width 5 6 7 10 ns
6 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H 30 t wcr write command hold time from ras 30 35 40 45 ns 31 t rwl write command to ras lead time 12 13 14 15 ns 32 t ds data in setup time 0 0 0 0 ns 14 33 t dh data in hold time 5 6 7 10 ns 14 34 t woh write to oe hold time 6 7 8 10 ns 14 35 t oed oe to data delay time 6 7 8 10 ns 14 36 t rwc read-modify-write cycle time 110 115 130 170 ns 37 t rrw read-modify-write cycle ras pulse width 75 80 87 105 ns 38 t cwd cas to we delay 30 32 34 40 ns 12 39 t rwd ras to we delay in read-modify- write cycle 58 62 68 85 ns 12 40 t crw cas pulse width (rmw) 48 50 52 65 ns 41 t awd col. address to we delay 38 41 42 58 ns 12 42 t pc fast page mode read or write cycle time 23 25 28 40 ns 43 t cp cas precharge time 5 6 7 8 ns 44 t car column address to ras setup time 20 22 24 30 ns 45 t cap access time from column precharge 23 25 27 34 ns 7 46 t dhr data in hold time referenced to ras 30 35 40 50 ns 47 t csr cas setup time cas -before- ras refresh 10 10 10 10 ns 48 t rpc ras to cas precharge time 0 0 0 0 ns 49 t chr cas hold time cas -before- ras refresh 8 10 12 15 ns 50 t pcm fast page mode read-modify-write cycle time 60 65 70 85 ns 51 t t transition time (rise and fall) 3 50 3 50 3 50 3 50 ns 15 52 t ref refresh interval (1024 cycles) 16 16 16 16 ms # symbol parameter 40 45 50 60 unit notes min. max. min. max. min. max. min. max. ac characteristics (cont?)
7 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i cc (max.) is measured with a maximum of two transitions per address cycle in fast page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to ?.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to two ttl inputs and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad ex- ceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns . 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
8 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of read cycle waveforms of early write cycle ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t ca c (18) t t hz (22) t hz (22) t lz (21) ih v il v we oh v ol v i/o v alid d a t a-out address ra c (19) column address r o w address t o a c (17) t hz (22) ih v il v oe t r oh (16) 806h-04 ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (1 1) t t rad (24) t rah (9) t asr (8) t t wcr (30) t r wl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v t t cwl (26) wch (28) t t ds (32) column address v alid d a t a-in high-z ras cas we oe i/o address t car (44) asc (10) wcs (27) wp (29) r o w address 806h-05 don? care undefined
9 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of oe -controlled write cycle waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) r o w address column address t w oh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v v alid d a t a-in t ds (32) t rad (24) ras cas we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) r wl (31) t cwl (26) t 806h-06 column address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) wp (29) r wl (31) t oed (35) t ih v il v ih v il v ih v il v v alid d a t a-out t ra c (19) t cwl (26) t t rad (24) t t o a c (17) t t dh (33) t ds (32) hz (22) ca c (18) t lz (21) v alid d a t a-in ih v il v oh ol ras cas we oe i/o address t r wc (36) t rr w (37) t ar (23) t csh (4) t rsh (w)(25) t cr w (40) t r wd (39) cwd (38) t a wd (41) t t caa (20) t rcs (17) r o w address 806h-07 don? care undefined
10 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of fast page mode read cycle waveforms of fast page mode write cycle v alid da t a out v alid da t a out column address cac (18) t t hz (22) hz (22) hz (22) hz (22) row address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 806h-08 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (1 1) t hz (22) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (1 1) t rcs (7) t rcs (7) t rch (14) t oac (17) t t t oac (17) t caa (20) t rrh (15) t hz (22) lz (21) t rac (19) t t cac (18) v alid da t a out t crp (13) t t lz (21) t ras cas we oe i/o address t asc (10) t lz (21) cac (18) t caa (20) oac (17) cap (45) t cah (1 1) row add ih v il v ih v il v ih v il v ih v il v t t asr (8) 806h-09 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) v alid da t a in t crp (13) t wcs (27) wp (29) t cah (1 1) t asc (10) t cah (1 1) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t v alid da t a in t dh (33) t ds (32) v alid da t a in t dh (33) t ds (32) t rp (3) t ar (23) ras cas we oe i/o address open open t r wl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) don? care undefined
11 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of fast page mode read-write cycle waveforms of ras -only refresh cycle rasp (37) r o w add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address ih v il v cp (43) t asc (10) rcd (6) t t t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t t t crp (13) t rcs (7) t cah (1 1) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t r wl (31) t a wd (41) t caa (20) t t o a c (17) t a wd (41) t o a c (17) in t ca c (18) t oed (35) t ds (32) t dh (33) t lz (21) in out hz (22) t oed (35) ds (32) t dh (33) t t cap (43) t t ca c (18) t caa (20) lz (21) in hz (22) t oed (35) ds (32) t dh (33) t t t ca c (18) t caa (20) cap (43) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras we oe i/o address t a wd (41) out ra c (19) t o a c (17) t r wd (39) cah (1 1) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out cas 806h-10 ih v il v ras ih v il v rp (3) t ih v il v cas t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 806h-11 we, oe = don? care note: address row addr don? care undefined
12 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of cas -before- ras refresh counter test cycle waveforms of cas -before- ras refresh cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 806h-12 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t cp (43) t cas (5) t rch (14) t rrh (15) t r oh (16) t o a c (17) t hz (22) t hz (22) t hz (22) t r wl (31) t cwl (26) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out ras cas oe oe t dh (33) t ds (32) d in i/o ih v il v ras oh v ol v ih v il v cas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) 806h-13 rp (3) t t rpc (48) t chr (49) rp (3) t we, oe, = don? care no te: a ? 0 9 don? care undefined
13 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) t chr (49) t rad (24) t asc (10) t t cah (1 1) r o w add column address t rrh (15) t o a c (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas we oe i/o address v alid d a t a rah (9) t caa (20) t ca c (18) t ra c (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) t hz (22) 806h-14 ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 806h-15 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (1 1) r o w add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v v alid d a t a-in t dhr (46) t rc (2) ras cas i/o address t dh (33) we oe don? care undefined
14 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H functional description the V53C806H is a cmos dynamic ram opti- mized for high data bandwidth, low power applica- tions. it is functionally similar to a traditional dynamic ram. the V53C806H reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. the row address is latched by the row address strobe ( ras ). the column address ?lows through?an internal address buffer and is latched by the column address strobe ( cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be end- ed or aborted before the minimum t ras time has ex- pired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas opera- tion. the column address must be held for a mini- mum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for exam- ple, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column ad- dress is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. fast page mode operation fast page mode operation permits all 1024 col- umns within a selected row of the device to be ran- domly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column ad- dress buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occurrence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer and acts as an output enable. during fast page mode opera- tion, read, write, read-modify-write or read- write-read cycles are possible at random address- es within a row. following the initial entry cycle into fast page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column address is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output. fast page mode provides a sustained data rate of 43 mhz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: data output operation the V53C806H input/output is controlled by oe , cas , we and ras . a ras low transition enables the transfer of data to and from the selected row ad- dress in the memory array. a ras high transition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initi- ated with a ras low transition, a cas low transition enables the internal i/o path. a cas high transition or ras high transition, whichever occurs later, dis- ables the i/o path and the output driver if it is en- abled. a cas low transition while ras is high has no effect on the i/o data path or on the output driv- ers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal data rate 1024 t r c 1023 t p c + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =
mosel vitelic V53C806H 15 V53C806H re v . 1.6 f ebr uar y 1999 has no effect on any data stored in the output latch- es. a we low level can also disable the output driv- ers. during a write cycle, if we goes low at a time when the cas is low, it is necessary to use oe to disable the output drivers prior to the we low tran- sition to allow data in setup time (t ds ) to be satis- fied. to retain data, 1024 refresh cycles are required in each 16 ms period. there are two ways to refresh the memory: 1. by clocking each of the 1024 row addresses (a 0 through a 9 ) with ras at least once every 16 ms. any read, write, read-modify-write or ras -only cycle refreshes the addressed row. 2. using a cas -before- ras refresh cycle. if cas makes a transition from low to high to low after the previous cycle and before ras falls, cas -before- ras refresh is activated. the V53C806H uses the output of an internal 10-bit counter as the source of row addresses and ignore external address inputs. cas -before- ras is a ?efresh-only?mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cy- cle. a cas -before- ras counter test mode is provid- ed to ensure reliable operation of the internal refresh counter. data retention mode the V53C806H offers a cmos standby mode that is entered by causing the ras clock to swing between a valid v il and an ?xtra high?v ih within 0.2 v of v cc . while the ras clock is at the extra high level, the V53C806H power consumption is re- duced to the low i cc6 level. overall i cc consump- tion when operating in this mode can be calculated as follows: where: t rc = refresh cycle time t rx = refresh interval/1024 power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the V53C806H is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i cc will exhibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih during power-on to avoid current surges. table 1. V53C806H data output operation for various cycle types i t r c ( ) i c c 1 ( ) t r x t r c ( ) i c c 6 ( ) + t r x - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = cycle type i/o state read cycles data from addressed memory cell cas -controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell fast page mode read data from addressed memory cell fast page mode write cycle (early write) high-z fast read-modify-write cycle data from addressed memory cell ras -only refresh high-z cas -before- ras refresh cycle data remains as in previous cycles cas -only cycles high-z
16 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H package diagrams 28-pin plastic soj 0.725 0.005 [18.42 0.12] +0.007 ?.006 0.004 [0.102] 0.025 min [.635 min] 0.138 0.400 0.005 [10.16 .0.13] 0.440 0.005 [1 1.18 0.12] 28 1 15 14 0.370 0.010 [9.40 0.26] unit in inches [mm] 0.028 0.015/0.020 [0.38/0.51] +0.004 ?.002 0.05 bsc 0.043 max [1.09 max] +0.178 ?.154 3.51 [1.27 bsc] +0.102 ?.051 0.71 1
17 V53C806H re v . 1.6 f ebr uar y 1999 mosel vitelic V53C806H
mosel vitelic w orld wide offices V53C806H mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?cop yr ight 1999, mosel vitelic inc. 2/99 pr inted in u .s .a. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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